Herzog Library 00.00.01  rel_libdev.herzog.00.00.01.10606
tx_sfrs.h
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1 
12 #ifndef __TX_SFRS_H__
13 #define __TX_SFRS_H__
14 
18 
19 //The procedures of RF transmission are as follows:
20 //1. Select ASK mode (for Krankl it only supports ASK mode)
21 //2. Set NX, NF for PLL to match 433.92MHZ
22 //3. Given burst bit number, wait bit number, chip rate
23 //4. Set timing of RF such as TPATCH, TED
24 //5, put first two bytes data into buffer and start TX
25 //6. TX will be interrupt by reload or burst done
26 
27 #define TXCTRL0_MODUL_ASK ((uint8_t) (0x03 << 4))
28 //#define TXCTRL0_MODUL_PSK ((uint8_t) (0x01 << 4))
29 //#define TXCTRL0_MODUL_FSK ((uint8_t) (0x02 << 4))
30 #define TXCTRL0_FRAC_EN ((uint8_t) (0x01 << 3))
31 #define TXCTRL0_NXTBURST ((uint8_t) (0x01 << 6))
32 #define TXCTRL0_STARTX ((uint8_t) (0x01 << 7))
33 #define TXCTRL1_PEDES_10 ((uint8_t) (0x00 << 6))
34 #define TXCTRL1_PEDES_12 ((uint8_t) (0x01 << 6))
35 #define TXCTRL1_PEDES_14 ((uint8_t) (0x02 << 6))
36 #define TXCTRL1_PEDES_16 ((uint8_t) (0x03 << 6))
37 
38 #define TXTRIM0_VAL ((uint8_t) 0x44)
39 #define TXTRIM1_VAL ((uint8_t) 0x82)
40 
93 typedef struct
94 {
95  __IO uint8_t TXCTRL0; // { STARTX , NXTBURST , MODUL[1:0] , FRAC_EN , RESERVED[2:0] }
96  __IO uint8_t TXCTRL1; // { PEDES[1:0] , TPATCH[10:5] }
97  __IO uint8_t POWLEV; // { POWLEV[7:0] }
98  __IO uint8_t POWAP; // { ASKAMP[7:0] }
100 
101 
102 
111 typedef union
112 {
113  __IO uint16_t HWORD;
114  __IO uint8_t BYTE[2];
115 } RFTX_DATAType;
116 
117 
128 typedef union
129 {
130  __IO uint16_t HWORD; // { NWAIT[5:0] , NXBITS[9:0] }
131  struct{
132  __IO uint8_t NBURST; // { NXBITS[7:0] }
133  __IO uint8_t TXCTRL2; // { NWAIT[5:0] , NXBITS[9:8] }
134  }BYTE;
136 
137 
138 
162 typedef union
163 {
164  __IO uint16_t HWORD[2]; // HWORD[1]=> { TDET3[2:0] , TDET4[4:0], TRAMP[3:0] , TDET2[2:0] , TDET1}
165  //HWORD[0]=> { TPATCH[4:0] , TXCLKDIV[10:0]}
166  struct{
167  __IO uint8_t TXCLKDIV; // {TXCLKDIV[7:0] }
168  __IO uint8_t TXCTRL3; //{ TPATCH[4:0] , TXCLKDIV[10:8] }
169  __IO uint8_t TXCTRL4; // { TRAMP[3:0] , TDET2[2:0] , TDET1}
170  __IO uint8_t TXCTRL5; //{ TDET3[2:0] , TDET4[4:0] }
171  }BYTE;
172 
174 
175 
176 
191 typedef union
192 {
193  __IO uint32_t WORD; // {DF[5:0], LPFTRIM[3:0], CPTRIM[2:0], NX[4:0], NF[13:0]}
194  __IO uint16_t HWORD[2]; // HWORD[1] ==> { DF[5:0] , LPFTRIM[3:0] , CPTRIM[2:0] , NX[4:2] }
195  // HWORD[0] ==> { NX[1:0] , NF[13:0] }
196  struct {
197  __IO uint8_t PLLCTRL0; // { NF[7:0] }
198  __IO uint8_t PLLCTRL1; // { NX[1:0] , NF[13:8] }
199  __IO uint8_t PLLCTRL2; // { LPFTRIM[1:0] , CPTRIM[2:0] , NX[4:2] }
200  __IO uint8_t PLLCTRL3; // { DF[5:0] , LPFTRIM[3:2] }
201  }BYTE;
202 } RFTX_PLLType;
203 
207 #define TX_BASE (ASIC_7B_BASE + 0x32)
208 
209 #define RFTX_CTRL ((RFTX_CTRLType *) (ASIC_7B_BASE + 0x32))
210 
211 #define RFTX_DATA ((RFTX_DATAType *) (ASIC_7B_BASE + 0x36))
212 
213 #define RFTX_MSGFMT ((RFTX_MSGFMTType *) (ASIC_7B_BASE + 0x38))
214 
215 
216 #define RFTX_TIMING ((RFTX_TIMINGType *) (ASIC_7B_BASE + 0x3A))
217 
218 
219 #define RFTX_PLL ((RFTX_PLLType *) (ASIC_16B_BASE + 0x8000))
220 
221 
224 #define TXTRIM0 ((__IO uint8_t *) (ASIC_16B_BASE + 0x03))
225 
226 #define TXTRIM1 ((__IO uint8_t *) (ASIC_16B_BASE + 0x0C))
227 
228 
229 
233 
234 static __INLINE void TX_StartTransmission()
235 {
236  RFTX_CTRL->TXCTRL0 |= TXCTRL0_STARTX;
237 
238 }
239 
240 static __INLINE void TX_StopTransmission()
241 {
242  RFTX_CTRL->TXCTRL0 &= ~TXCTRL0_STARTX;
243 }
244 
245 static __INLINE void TX_En_NextBurst()
246 {
247  RFTX_CTRL->TXCTRL0 |= TXCTRL0_NXTBURST;
248 }
249 
250 static __INLINE void TX_Dis_NextBurst()
251 {
252  RFTX_CTRL->TXCTRL0 &= ~TXCTRL0_NXTBURST;
253 }
254 
267 static __INLINE void TX_TXconfig(uint8_t module, uint8_t frac_en, uint8_t peds)
268 {
269  RFTX_CTRL->TXCTRL0 = (module | frac_en);
270  RFTX_CTRL->TXCTRL1 |= peds;
271 }
272 
279 static __INLINE void TX_SetPowerLevel(uint8_t powlev, uint8_t powap)
280 {
281  RFTX_CTRL->POWLEV = powlev;
282  RFTX_CTRL->POWAP = powap;
283 }
288 static __INLINE void TX_SetTpatch(uint16_t tpatch)
289 {
290  RFTX_CTRL->TXCTRL1 |= ((uint8_t)(tpatch>>5) & 0x3F);
291  RFTX_TIMING->BYTE.TXCTRL3 |= ((uint8_t)(tpatch << 3));
292 }
293 
299 static __INLINE void TX_SetMsgFormat(uint16_t nburst, uint8_t nwait)
300 {
301  RFTX_MSGFMT->HWORD = (nwait<<10 & 0xFC00)|(nburst & 0x03FF);
302 }
303 
310 static __INLINE void TX_SetChipRate(uint16_t txcdiv)
311 {
312  RFTX_TIMING->HWORD[0] |= (0x07FF & txcdiv);
313 }
314 
324 static void TX_SetTiming(uint16_t txcdiv, uint16_t nburst, uint8_t nwait_total)
325 {
326  uint8_t NWAIT = (uint8_t)(nwait_total - 340.0 / (4 * txcdiv));
327  uint16_t TPATCH = (uint16_t)(((nwait_total - NWAIT) * txcdiv *4/5 - 68 - 0.8 ) / 0.781);
328  TX_SetTpatch(TPATCH);
329  TX_SetMsgFormat(nburst, NWAIT);
330  TX_SetChipRate(txcdiv);
331  RFTX_TIMING->HWORD[1] = 0xB404; //default TED value
332 }
333 
338 static __INLINE void TX_SetFreq()
339 {
340  RFTX_PLL->WORD = 0x00C95E04;
341 }
342 
343 static __INLINE void TX_LoadData(uint16_t data)
344 {
345  RFTX_DATA->HWORD = data;
346 }
347 
348 #endif /* __TX_SFRS_H__ */
__IO uint16_t HWORD
Definition: tx_sfrs.h:113
static __INLINE void TX_StartTransmission()
RF Transmitter Function.
Definition: tx_sfrs.h:234
__IO uint8_t PLLCTRL0
Definition: tx_sfrs.h:197
static void TX_SetTiming(uint16_t txcdiv, uint16_t nburst, uint8_t nwait_total)
: given the number of wait bit time and using default TED value to calculate the value of NWAIT[5:0] ...
Definition: tx_sfrs.h:324
#define TXCTRL0_STARTX
Definition: tx_sfrs.h:32
__IO uint8_t PLLCTRL3
Definition: tx_sfrs.h:200
#define RFTX_TIMING
Definition: tx_sfrs.h:216
static __INLINE void TX_SetMsgFormat(uint16_t nburst, uint8_t nwait)
RF TX set message format including burst bit and wait bit time.
Definition: tx_sfrs.h:299
#define RFTX_DATA
Definition: tx_sfrs.h:211
__IO uint32_t WORD
Definition: tx_sfrs.h:193
Definition: tx_sfrs.h:162
static __INLINE void TX_Dis_NextBurst()
Definition: tx_sfrs.h:250
static __INLINE void TX_LoadData(uint16_t data)
Definition: tx_sfrs.h:343
__IO uint8_t PLLCTRL2
Definition: tx_sfrs.h:199
Definition: tx_sfrs.h:191
__IO uint8_t PLLCTRL1
Definition: tx_sfrs.h:198
static __INLINE void TX_SetPowerLevel(uint8_t powlev, uint8_t powap)
RF TX amplifier power.
Definition: tx_sfrs.h:279
static __INLINE void TX_StopTransmission()
Definition: tx_sfrs.h:240
__IO uint8_t TXCTRL4
Definition: tx_sfrs.h:169
#define RFTX_PLL
Definition: tx_sfrs.h:219
#define RFTX_CTRL
Definition: tx_sfrs.h:209
RF Transmitter Structure.
Definition: tx_sfrs.h:93
__IO uint8_t NBURST
Definition: tx_sfrs.h:132
Definition: tx_sfrs.h:128
Definition: tx_sfrs.h:111
__IO uint8_t TXCLKDIV
Definition: tx_sfrs.h:167
static __INLINE void TX_SetChipRate(uint16_t txcdiv)
RF TX clock divider number chip rate = 1.25Mbps / TXCLKDIV for example, if chip rate is 3...
Definition: tx_sfrs.h:310
__IO uint8_t TXCTRL2
Definition: tx_sfrs.h:133
#define TXCTRL0_NXTBURST
Definition: tx_sfrs.h:31
__IO uint8_t TXCTRL3
Definition: tx_sfrs.h:168
static __INLINE void TX_TXconfig(uint8_t module, uint8_t frac_en, uint8_t peds)
RF TX Control.
Definition: tx_sfrs.h:267
__IO uint8_t TXCTRL1
Definition: tx_sfrs.h:96
__IO uint8_t POWLEV
Definition: tx_sfrs.h:97
__IO uint8_t TXCTRL0
Definition: tx_sfrs.h:95
static __INLINE void TX_SetFreq()
: Set TX frequency The default value is for RF Freq: 433.92Mhz at XTAL Freq 30MHz.
Definition: tx_sfrs.h:338
#define RFTX_MSGFMT
Definition: tx_sfrs.h:213
static __INLINE void TX_En_NextBurst()
Definition: tx_sfrs.h:245
__IO uint8_t TXCTRL5
Definition: tx_sfrs.h:170
__IO uint8_t POWAP
Definition: tx_sfrs.h:98
__IO uint16_t HWORD
Definition: tx_sfrs.h:130
static __INLINE void TX_SetTpatch(uint16_t tpatch)
RF TX set patch time.
Definition: tx_sfrs.h:288