Herzog Library 00.00.01  rel_libdev.herzog.00.00.01.10606
clough_core.h
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1 // ********************************************************************************************************************
2 // Header file for generic Clough functions
3 // ********************************************************************************************************************
4 
5 #ifndef __CLOUGH_MCU_H__
6 #define __CLOUGH_MCU_H__
7 
8 // ********************************************************************************************************************
9 // Number of IRQ priority level bits - must be defined before loading core_cm0.h
10 // ********************************************************************************************************************
11 
12 #define __NVIC_PRIO_BITS 2
13 
14 // ********************************************************************************************************************
15 // Includes
16 // ********************************************************************************************************************
17 #include "core_cm0.h"
18 #include <stdint.h>
19 
20 // ********************************************************************************************************************
21 // Base addresses
22 // ********************************************************************************************************************
23 
24 #define FLASH_BASE ((uint32_t) 0x00000000)
25 #define SRAM_BASE ((uint32_t) 0x20000000)
26 #define SRAM_TOP ((uint32_t) 0x20001FFF)
27 #define PERIPH_BASE ((uint32_t) 0x40000000)
28 #define SDIO_BASE ((uint32_t) 0x50000000)
29 #define ASIC_7B_BASE ((uint32_t) 0x50000000)
30 #define BTE_BASE ((uint32_t) 0x50000080)
31 #define ASIC_16B_BASE ((uint32_t) 0x50010000)
32 #define TIMER_BASE ((uint32_t) 0x50020000)
33 #define FLASH_CTRL_BASE ((uint32_t) 0x50020020)
34 
35 #define FLASH_1ST_SECTOR (FLASH_BASE + 0x40000)
36 #define FLASH_2ND_SECTOR (FLASH_BASE + 0x40100)
37 
38 // ********************************************************************************************************************
39 // Peripheral addresses
40 // ********************************************************************************************************************
41 
42 // Flash programming addresses
43 #define FLASH_ACCESS_ADDR ((volatile uint32_t *) (FLASH_CTRL_BASE + 0x00))
44 #define FLASH_PROGRESS_FLAGS ((volatile uint8_t *) (FLASH_CTRL_BASE + 0x01))
45 #define FLASH_WRITE_DATA ((volatile uint8_t *) (FLASH_CTRL_BASE + 0x04))
46 #define FLASH_UNLOCK_BYTE_WRITE ((volatile uint32_t *) (FLASH_CTRL_BASE + 0x08))
47 #define FLASH_BYTE_WRITE ((volatile uint32_t *) (FLASH_CTRL_BASE + 0x0C))
48 #define FLASH_UNLOCK_SECTOR_ERASE ((volatile uint32_t *) (FLASH_CTRL_BASE + 0x10))
49 #define FLASH_SECTOR_ERASE ((volatile uint32_t *) (FLASH_CTRL_BASE + 0x14))
50 #define FLASH_UNLOCK_BLOCK_ERASE ((volatile uint32_t *) (FLASH_CTRL_BASE + 0x18))
51 #define FLASH_BLOCK_ERASE ((volatile uint32_t *) (FLASH_CTRL_BASE + 0x1C))
52 #define FLASH_ACCESS_CFG ((volatile uint32_t *) (FLASH_CTRL_BASE + 0x20))
53 #define CODE_PROT_REG ((volatile uint32_t *) (FLASH_CTRL_BASE + 0x24))
54 #define CODE_PROT_PAT ((volatile uint32_t *) (FLASH_CTRL_BASE + 0x24))
55 
56 // Flash config words
57 #define FLASH_CONFIG_W0 ((volatile uint32_t *) (FLASH_2ND_SECTOR + 0x00))
58 #define FLASH_CONFIG_W1 ((volatile uint32_t *) (FLASH_2ND_SECTOR + 0x04))
59 
60 // Special AyDeeKay flash sector
61 #define FLASH_ADK_SECTOR ((uint32_t) (FLASH_BASE + 0x27F00 ))
62 
63 // Block transfer engine
64 #define BTE_CFG ((volatile uint32_t *) (BTE_BASE + 0x00))
65 #define BTE_SFR_ADDR ((volatile uint16_t *) (BTE_BASE + 0x00))
66 #define BTE_NUM_XFER ((volatile uint8_t *) (BTE_BASE + 0x02))
67 #define BTE_CMD ((volatile uint8_t *) (BTE_BASE + 0x03))
68 #define BTE_SRAM_ADDR ((volatile uint32_t *) (BTE_BASE + 0x04))
69 
70 // General purpose timers
71 
72 typedef struct {
73  __IO int32_t COUNT;
74  __IO uint8_t CFG;
75 } Timer_Type;
76 
77 typedef struct {
78  __IO uint8_t CFG;
79  __IO uint8_t empty1;
80  __IO uint8_t empty2;
81  __IO uint8_t empty8;
82  __O uint32_t KEY;
84 
85 #define TIMER0 ((Timer_Type *) (TIMER_BASE + 0x00))
86 #define TIMER1 ((Timer_Type *) (TIMER_BASE + 0x08))
87 #define TIMER2 ((Timer_Type *) (TIMER_BASE + 0x0C))
88 
89 //#define TIMER0_VAL ((volatile int32_t *) (TIMER_BASE + 0x00))
90 //#define TIMER0_CFG ((volatile uint8_t *) (TIMER_BASE + 0x04))
91 //#define TIMER1_VAL ((volatile int32_t *) (TIMER_BASE + 0x08))
92 //#define TIMER1_CFG ((volatile uint8_t *) (TIMER_BASE + 0x0C))
93 //#define TIMER2_VAL ((volatile int32_t *) (TIMER_BASE + 0x10))
94 //#define TIMER2_CFG ((volatile uint8_t *) (TIMER_BASE + 0x14))
95 
96 // Watchdog timer
97 #define WATCHDOG ((__IO Watchdog_Type *) (TIMER_BASE + 0x18))
98 //#define WATCHDOG_CFG_REG ((volatile uint8_t *) (TIMER_BASE + 0x18))
99 //#define WATCHDOG_CLR_REG ((volatile uint32_t *) (TIMER_BASE + 0x1C))
100 
101 
102 // ********************************************************************************************************************
103 // Key Words
104 // ********************************************************************************************************************
105 
106 // Flash unlock values
107 #define FLASH_UNLOCK_BYTE_WRITE_KEY ((uint32_t) 0x55555555)
108 #define FLASH_BYTE_WRITE_KEY ((uint32_t) 0xAAAAAAAA)
109 #define FLASH_UNLOCK_BLOCK_ERASE_KEY ((uint32_t) 0x77777777)
110 #define FLASH_BLOCK_ERASE_KEY ((uint32_t) 0x88888888)
111 #define FLASH_UNLOCK_SECTOR_ERASE_KEY ((uint32_t) 0x66666666)
112 #define FLASH_SECTOR_ERASE_KEY ((uint32_t) 0x99999999)
113 #define FLASH_ADKBYTE_WRITE_KEY ((uint32_t) 0x502901FF)
114 #define FLASH_ADKSECTOR_ERASE_KEY ((uint32_t) 0x502901FF)
115 
116 // Code protection lock value
117 #define CODE_PROTECT_KEY ((uint32_t) 0xF2E11047)
118 
119 // Watchdog
120 #define WATCHDOG_KEY0 ((uint32_t) 0x3C570001)
121 #define WATCHDOG_KEY1 ((uint32_t) 0x007F4AD6)
122 #define WATCHDOG_KEY_CLEAR ((uint32_t) 0x00000000)
123 
124 
125 // ********************************************************************************************************************
126 // Bit indexing helpers
127 // ********************************************************************************************************************
128 
129 // Flash progress flags
130 #define FLASH_WRITE_IN_PROGRESS ((uint8_t) 0x01)
131 #define FLASH_SECTOR_ERASE_IN_PROGRESS ((uint8_t) 0x02)
132 #define FLASH_BLOCK_ERASE_IN_PROGRESS ((uint8_t) 0x04)
133 
134 // Block transfer engine (bit masks for BTE_CMD)
135 #define BTE_START_CMD (((uint8_t) 1) << 3)
136 #define BTE_BLOCKING_XFER_CMD (((uint8_t) 1) << 2)
137 #define BTE_WRITE_CMD (((uint8_t) 1) << 1)
138 #define BTE_ADDR_INCR_CMD (((uint8_t) 1) << 0)
139 
140 // ********************************************************************************************************************
141 // Include CortexM0 core functions. Must be done after interrupt enums.
142 // ********************************************************************************************************************
143 
144 // #include "core_cm0.h"
145 
146 #endif
__IO uint8_t CFG
Definition: clough_core.h:74
Definition: clough_core.h:72
__O uint32_t KEY
Definition: clough_core.h:82
Definition: clough_core.h:77
__IO uint8_t empty2
Definition: clough_core.h:80
__IO uint8_t empty8
Definition: clough_core.h:81
__IO uint8_t CFG
Definition: clough_core.h:78
__IO uint8_t empty1
Definition: clough_core.h:79
__IO int32_t COUNT
Definition: clough_core.h:73