Herzog Library 00.00.01
rel_libdev.herzog.00.00.01.10606
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#include <tx_sfrs.h>
Data Fields | |
__IO uint16_t | HWORD [2] |
struct { | |
__IO uint8_t TXCLKDIV | |
__IO uint8_t TXCTRL3 | |
__IO uint8_t TXCTRL4 | |
__IO uint8_t TXCTRL5 | |
} | BYTE |
RFTX_TIMING: TX timing control
TPATCH[4:0]: see description in TXCONFIG section
TXCLKDIV: controls chip rate for the rf message. This number multiplied by approximately 800ns to determine the duration of each transmitted chip.
TDET1: controls time between analog bias enable and PLL enable (bias settling time). 0 => 1.6 us (recommended) 1 => 8.0 us
TDET2: controls time between PLL enable and PA enable (PLL settling time). The delay is (1+TDET2*1024)*800ns. Recommended value is 3'b010.
TDET3: controls the time between PA enable and power ramp up (pedestal time). The delay is (1+TDET3*1024)*800ns. Recommended value is 3'b101.
TDET4: controls the time between power ramp up and initiation of modulation (power level settling). The delay is (1+TDET4*1024)*800ns. Recommended value is 5'b10100.
struct { ... } BYTE |
__IO uint16_t HWORD[2] |
__IO uint8_t TXCLKDIV |
__IO uint8_t TXCTRL3 |
__IO uint8_t TXCTRL4 |
__IO uint8_t TXCTRL5 |