15 #define RX_BUFF_SIZE 16
20 #define RX_BASE (ASIC_7B_BASE + 0x20)
21 #define RX_SAP_BASE (ASIC_16B_BASE + 0x1000)
22 #define TRIM_SAP_BASE (ASIC_16B_BASE + 0x8004)
25 #define RFEN 0x80 //RF is ON
26 #define RFOFF 0x00 //RF is OFF
28 #define SNIFEN 0x40 //Sniffer enable
29 #define SNIFDIS 0x00 //Sniffer disable
30 #define MSGRDY 0x20 //Define message ready: Reading returns one if
37 #define AGCOVF 0x10 //AGC overflow flag: Returns one if an overflow
42 #define SLICEROUT 0x02 //Slicer output
43 #define RFSLEEP 0x01 //RF reception in sleep
45 #define LOWBPS 0x80 // Count bit times at half rate
46 #define NORMALBPS 0x00 // NOrmal BPS
48 #define AGCEN 0x80 // AGC enabled or fixed gain (disabled)
68 #define ALPHA00 0x00 //Delay timer of the slicer
69 #define ALPHA01 (0x01<<6)
70 #define ALPHA02 (0x02<<6)
71 #define ALPHA03 (0x03<<6)
72 #define BETA00 0x00 //Attack time of the slicer
73 #define BETA01 (0x01<<4)
74 #define BETA02 (0x02<<4)
75 #define BETA03 (0x03<<4)
76 #define FT00 0x00 //Time to allow slicer to fast bias
77 #define FT01 (0x01<<2)
78 #define FT02 (0x02<<2)
79 #define FT03 (0x03<<2)
80 #define SDR00 0x00 //Symbol Decimation rate
86 #define PLL32 (0x00<<6) //Controls the time to wait for PLL to bias, measured in clock cycles of the Fxo/64:
87 #define PLL48 (0x01<<6) //00 => 32 cycles (570us for 3.58MHz crystal)
88 #define PLL64 (0x02<<6) //01 => 48 cycles (860us for 3.58 MHz crystal)
89 #define PLL128 (0x03<<6) //10 => 64 cycles (1.15ms for 3.58 MHz crystal)
91 #define RFSLEEP4 (0x00<<3) //Controls the time sleep between sniff cycles, measured in clock cycles of the fXO/64:
92 #define RFSLEEP6 (0x01<<3) //000 => 4*1024 cycles (73ms for 3.58MHz crystal)
93 #define RFSLEEP8 (0x02<<3) //001 => 6*1024 cycles (110ms for 3.58 MHz crystal)
94 #define RFSLEEP10 (0x03<<3) //010 => 8*1024 cycles (146ms for 3.58MHz crystal)
95 #define RFSLEEP12 (0x04<<3) //011 => 10*1024 cycles (183ms for 3.58MHz crystal)
96 #define RFSLEEP14 (0x05<<3) //100 => 12*1024 cycles (220ms for 3.58MHz crystal)
97 #define RFSLEEP32 (0x06<<3) //101 => 14*1024 cycles (256ms for 3.58 MHz crystal)
98 #define RFSLEEP128 (0x07<<3) //110 => 32*1024 cycles (586ms for 3.58MHz crystal)
100 #define WAKET8 0x00 //Controls the time to stay awake after seeing a valid guardband, measured in clock cycles of the fXO/64:
101 #define WAKET10 0x01 //000 => 8*1024 cycles (146ms for 3.58MHz crystal)
102 #define WAKET12 0x02 //001 => 10*1024 cycles (183ms for 3.58 MHz crystal)
103 #define WAKET14 0x03 //010 => 12*1024 cycles (220ms for 3.58MHz crystal)
104 #define WAKET16 0x04 //011 => 14*1024 cycles (256ms for 3.58MHz crystal)
105 #define WAKET18 0x05 //100 => 16*1024 cycles (293ms for 3.58MHz crystal)
106 #define WAKET24 0x06 //101 => 18*1024 cycles (330ms for 3.58 MHz crystal)
107 #define WAKET32 0x07 //110 => 24*1024 cycles (440ms for 3.58MHz crystal)
111 #define RTSUP 0x00 //Selects a source for real-time output:
112 #define RTDE (0x01<<6) //00 => supervisor clock
113 #define RTSLICER (0x02<<6) //01 => decimator output (serialized stream)
114 #define RTPLL (0x03<<6) //10 => slicer output
117 #define RFONEN (0x01<<5)
122 #define HISDEN 0x80 //Controls image reject mixer to control whether
125 #define FEN 0x40 //If one then the PLL is used in fractional-N mode,
128 #define CPT00 0x00 //Charge pump current trim (settling time)
129 #define CPT01 (0x01<<4) //
130 #define CPT02 (0x02<<4) //
131 #define CPT03 (0x03<<4) //
134 #define DIV_LO2_15 (0x00<<6) //Controls the divide value of second LO. Divide value =
135 #define DIV_LO2_16 (0x01<<6) //16 +DIV_LO2[1:0]
136 #define DIV_LO2_17 (0x02<<6)
137 #define DIV_LO2_18 (0x03<<6)
138 #define BBGAIN0dB (0x00<<4) //Base band gain 00 = 0dB; 01 = 6dB; 10 = 12dB; 11 =
139 #define BBGAIN6dB (0x01<<4) //18dB
140 #define BBGAIN12dB (0x02<<4)
141 #define BBGAIN18dB (0x03<<4)
142 #define LNADR1K (0x01<<3) //LNA drain resistor 0 = 2Kohms, 1 = 1Kohm
143 #define LNADR2K (0x00<<3) //
144 #define LNABIAS0uA (0x00) //LNA bias current. 000 = 0; 001 = 200uA; 010 = 500uA;
145 #define LNABIAS200uA (0x01) //011 = 700uA; 100 = 1mA; 101 = 1.2mA; 110 = 1.5mA
146 #define LNABIAS500uA (0x02) //111 = 1.7mA
147 #define LNABIAS700uA (0x03)
148 #define LNABIAS1mA (0x04)
149 #define LNABIAS1p2mA (0x05)
150 #define LNABIAS1p5mA (0x06)
151 #define LNABIAS1p7mA (0x07)
191 __IO uint16_t HWORD[2];
204 #define RFRX_DATA ((RFRX_DATAType *) (RX_BASE + 0x00)) //RF RX Data received
205 #define RFRX ((RFRXType *) (RX_BASE + 0x10)) //RF RX status return
207 #define RFRX_CTRL ((RFRX_CTRLType *) (RX_SAP_BASE + 0x0000)) //RF RX control
209 #define RFRX_MONTR ((RFRX_MONTRType *) (RX_SAP_BASE + 0x0007)) //RF monitor
212 #define RFRX_PLL ((RFRX_PLLType *) (TRIM_SAP_BASE + 0x00)) // PLL Control to match the RX Freq
356 static __INLINE
void RX_SlicerControl( uint8_t alpha, uint8_t beta , uint8_t ft , uint8_t sdr )
358 RFRX_CTRL->SLCCTRL = alpha | beta | ft | sdr;
448 return ( ( uint8_t ) (
RFRX_CTRL->DCDTIME >> 12 ) );
469 return ( (uint8_t) ((
RFRX_CTRL->DCDTIME >> 6 ) & 0x003F ));
490 return ( (uint8_t) (
RFRX_CTRL->DCDTIME & 0x003F) );
507 static __INLINE
void RX_SetSnifRt( uint8_t rt, uint8_t rfall, uint8_t sniff )
531 static __INLINE
void RX_Setup0( uint8_t rejection, uint8_t fractional, uint8_t cpt, uint8_t lfrt )
544 static __INLINE
void RX_Setup1( uint8_t lodiv, uint8_t bbg, uint8_t lnadr, uint8_t lnab )
546 RFRX_PLL->BYTE.FETRIM1 = lodiv | bbg | lnadr | lnab;
static __INLINE void RX_SetMinBitNumber(uint8_t numbits)
Set RF Minimum number of bits.
Definition: rx_sfrs.h:319
__IO uint16_t SIGI
Definition: rx_sfrs.h:182
__IO uint8_t SYSTIME
Definition: rx_sfrs.h:174
static __INLINE void RX_SetMinTe(uint8_t minte)
Set Min_Te timer.
Definition: rx_sfrs.h:436
__IO uint8_t FETRIM1
Definition: rx_sfrs.h:197
static __INLINE uint8_t RX_ReadSleepTime(void)
Read sleep time between sniffs.
Definition: rx_sfrs.h:400
static __INLINE void RX_SnifferMode(uint8_t mode)
RF Sniffer Control (ON/OFF)
Definition: rx_sfrs.h:252
__IO uint16_t SIGQ
Definition: rx_sfrs.h:183
__IO uint32_t WORD
Definition: rx_sfrs.h:190
#define RFRX_MONTR
Definition: rx_sfrs.h:209
static __INLINE void RX_SetWakeTime(uint8_t wtime)
Set wake time in sniffs.
Definition: rx_sfrs.h:410
static __INLINE void RX_SetState(uint8_t state)
Set RF State (ON/OFF)
Definition: rx_sfrs.h:238
static __INLINE uint8_t RX_ReadAgc(void)
Read AGC gain value.
Definition: rx_sfrs.h:517
static __INLINE uint8_t RX_ReadMinTe(void)
Read Min_Te timer.
Definition: rx_sfrs.h:446
__IO uint16_t SLCHI
Definition: rx_sfrs.h:184
#define LOWBPS
Definition: rx_sfrs.h:45
static __INLINE void RX_SlicerControl(uint8_t alpha, uint8_t beta, uint8_t ft, uint8_t sdr)
Slicer control.
Definition: rx_sfrs.h:356
#define AGCOVF
Definition: rx_sfrs.h:37
#define FEN
Definition: rx_sfrs.h:125
static __INLINE uint8_t RX_MessageReady(void)
RF Message Ready.
Definition: rx_sfrs.h:266
Definition: rx_sfrs.h:188
__IO uint16_t DCDTIME
Definition: rx_sfrs.h:175
Definition: rx_sfrs.h:163
static __INLINE void RX_Setup0(uint8_t rejection, uint8_t fractional, uint8_t cpt, uint8_t lfrt)
RF Control 0.
Definition: rx_sfrs.h:531
Definition: rx_sfrs.h:169
static __INLINE uint8_t RX_ReadMaxTe(void)
Read Max_Te timer.
Definition: rx_sfrs.h:467
#define RTPLL
Definition: rx_sfrs.h:114
__IO uint16_t SLCLO
Definition: rx_sfrs.h:185
static __INLINE void RX_SetMaxTe(uint8_t maxte)
Set Max_Te timer.
Definition: rx_sfrs.h:457
static __INLINE uint8_t RX_ReadState(void)
RF Receiver Function.
Definition: rx_sfrs.h:226
__IO uint8_t NX
Definition: rx_sfrs.h:194
#define RFRX
Definition: rx_sfrs.h:205
__IO uint8_t AGCCTRL
Definition: rx_sfrs.h:172
__IO uint8_t AGCMON
Definition: rx_sfrs.h:181
__IO uint8_t NBMIN
Definition: rx_sfrs.h:171
Definition: rx_sfrs.h:179
#define HISDEN
Definition: rx_sfrs.h:122
#define MSGRDY
Definition: rx_sfrs.h:30
#define RFONEN
Definition: rx_sfrs.h:117
__IO uint8_t NUMB
Definition: rx_sfrs.h:165
static __INLINE void RX_SetSleepTime(uint8_t stime)
Set sleep time between sniffs.
Definition: rx_sfrs.h:389
static __INLINE uint8_t RX_ReadPllBiasTime(void)
Read time to wait for PLL bias.
Definition: rx_sfrs.h:378
static __INLINE uint8_t RX_ReadMinBitNumber(void)
Read RF Minimum number of bits.
Definition: rx_sfrs.h:330
#define AGCEN
Definition: rx_sfrs.h:48
static __INLINE uint8_t RX_ReadMinGb(void)
Read Min_Gb timer.
Definition: rx_sfrs.h:488
static __INLINE uint8_t RX_AgcOverflow(void)
RF ACG Overflow.
Definition: rx_sfrs.h:284
static __INLINE void RX_BitRateControl(uint8_t rate)
RF Bit Timing rate control.
Definition: rx_sfrs.h:296
__IO uint8_t STATUS
Definition: rx_sfrs.h:166
RF Receiver Structure.
Definition: rx_sfrs.h:156
static __INLINE uint8_t RX_ReadBitRateControl(void)
RF Bit Timing rate read.
Definition: rx_sfrs.h:308
static __INLINE void RX_SetMinGb(uint8_t mingb)
Set Min_Gb timer.
Definition: rx_sfrs.h:478
static __INLINE uint8_t RX_ReadWakeTime(void)
Read wake time in sniffs.
Definition: rx_sfrs.h:420
static __INLINE void RX_Setup1(uint8_t lodiv, uint8_t bbg, uint8_t lnadr, uint8_t lnab)
RF Control 1.
Definition: rx_sfrs.h:544
#define RFRX_CTRL
Definition: rx_sfrs.h:207
static __INLINE void RX_SetSnifRt(uint8_t rt, uint8_t rfall, uint8_t sniff)
Set Sniffer mode timing.
Definition: rx_sfrs.h:507
__IO uint8_t SNIFMODE
Definition: rx_sfrs.h:176
__IO uint8_t FETRIM0
Definition: rx_sfrs.h:196
#define RFRX_PLL
Definition: rx_sfrs.h:212
__IO uint8_t NF
Definition: rx_sfrs.h:195
static __INLINE void RX_AgcControl(uint8_t mode, uint8_t trim)
AGC control and trim.
Definition: rx_sfrs.h:342
#define RX_BUFF_SIZE
Definition: rx_sfrs.h:15
__IO uint8_t SLCCTRL
Definition: rx_sfrs.h:173
static __INLINE void RX_ReinitDecoder(void)
RF Reinit Decoder.
Definition: rx_sfrs.h:274
#define RFEN
Definition: rx_sfrs.h:25
#define SNIFEN
Definition: rx_sfrs.h:28
static __INLINE void RX_SetPllBiasTime(uint8_t btime)
Set time to wait for PLL bias.
Definition: rx_sfrs.h:368