Herzog Library 00.00.01  rel_libdev.herzog.00.00.01.10606
spi_sfrs.h
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1 
12 #ifndef __SPI_SFRS_H__
13 #define __SPI_SFRS_H__
14 
18 typedef struct {
19  union {
20  struct {
21  uint8_t SCKSTD:2;
22  uint8_t CPHA:1;
23  uint8_t CPOL:1;
24  uint8_t MSTR:1;
25  uint8_t Reserved:2;
26  uint8_t SINTE:1;
27  };
28  uint8_t SPCR;
29  } SPCR;
30  union {
31  struct {
32  uint8_t SRXFE:1;
33  uint8_t SRXFF:1;
34  uint8_t STXFE:1;
35  uint8_t STXFF:1;
36  uint8_t Reserved:2;
37  uint8_t SWCOL:1;
38  uint8_t SINTF:1;
39  };
40  uint8_t SPSR;
41  } SPSR;
42  uint8_t SPDR;
43  union {
44  struct {
45  uint8_t SCKEXT:2;
46  uint8_t SPE:1;
47  uint8_t Reserved:3;
48  uint8_t SICNT:2;
49  };
50  uint8_t SPER;
51  } SPER;
52 } SPI_SFRS_t;
53 
57 #define SPI_SFRS ((__IO SPI_SFRS_t *) (0x5000001C))
58 
59 #define E_SPI_CLOCK_DIV2 0
60 #define E_SPI_CLOCK_DIV4 1
61 #define E_SPI_CLOCK_DIV8 0
62 #define E_SPI_CLOCK_DIV16 2
63 #define E_SPI_CLOCK_DIV32 3
64 #define E_SPI_CLOCK_DIV64 1
65 #define E_SPI_CLOCK_DIV128 2
66 #define E_SPI_CLOCK_DIV256 3
67 #define E_SPI_CLOCK_DIV512 0
68 #define E_SPI_CLOCK_DIV1024 1
69 #define E_SPI_CLOCK_DIV2048 2
70 #define E_SPI_CLOCK_DIV4096 3
71 
72 #define E_SPI_CLOCK_EXT_DIV2 0
73 #define E_SPI_CLOCK_EXT_DIV4 0
74 #define E_SPI_CLOCK_EXT_DIV8 1
75 #define E_SPI_CLOCK_EXT_DIV16 0
76 #define E_SPI_CLOCK_EXT_DIV32 0
77 #define E_SPI_CLOCK_EXT_DIV64 1
78 #define E_SPI_CLOCK_EXT_DIV128 1
79 #define E_SPI_CLOCK_EXT_DIV256 1
80 #define E_SPI_CLOCK_EXT_DIV512 2
81 #define E_SPI_CLOCK_EXT_DIV1024 2
82 #define E_SPI_CLOCK_EXT_DIV2048 2
83 #define E_SPI_CLOCK_EXT_DIV4096 2
84 
85 #define E_SPI_CLOCK_PHASE0 0
86 #define E_SPI_CLOCK_PHASE1 1
87 
88 #define E_SPI_CLOCK_POLARITY0 0
89 #define E_SPI_CLOCK_POLARITY1 1
90 
91 #define E_SPI_STATUS_INTERRUPT ()uint8_t) (1<<7))
92 #define E_SPI_STATUS_WRITE_COLLISIION ((uint8_t) (1<<6))
93 #define E_SPI_STATUS_TX_FIFO_FULL ((uint8_t) (1<<3))
94 #define E_SPI_STATUS_TX_FIFO_EMPTY ((uint8_t) (1<<2))
95 #define E_SPI_STATUS_RX_FIFO_FULL ((uint8_t) (1<<1))
96 #define E_SPI_STATUS_RX_FIFO_EMPTY ((uint8_t) (1<<0))
97 
98 #define E_SPI_INT_DELAY_COUNT0 0
99 #define E_SPI_INT_DELAY_COUNT1 1
100 #define E_SPI_INT_DELAY_COUNT2 2
101 #define E_SPI_INT_DELAY_COUNT3 3
102 
109 static __INLINE void f_SPI_ClockDiv(uint8_t div, uint8_t ext_div)
110 {
111  SPI_SFRS->SPCR.SCKSTD = div;
112  SPI_SFRS->SPER.SCKEXT = ext_div;
113 }
114 
118 static __INLINE void f_SPI_SetPhase(uint8_t phase)
119 {
120  SPI_SFRS->SPCR.CPHA = phase;
121 }
122 
126 static __INLINE void f_SPI_SetPolarity(uint8_t Polarity)
127 {
128  SPI_SFRS->SPCR.CPOL = Polarity;
129 }
130 
134 static __INLINE void f_SPI_SetMode(uint8_t mode)
135 {
136  SPI_SFRS->SPCR.MSTR = mode;
137 }
138 
142 static __INLINE void f_SPI_IRQDelay(uint8_t cnt)
143 {
144  SPI_SFRS->SPER.SICNT = cnt;
145 }
146 
150 static __INLINE void f_SPI_Enable(void)
151 {
152  SPI_SFRS->SPER.SPE = 1;
153 }
154 
158 static __INLINE void f_SPI_Disable(void)
159 {
160  SPI_SFRS->SPER.SPE = 0;
161 }
162 
166 static __INLINE void f_SPI_IRQEnable(void)
167 {
168  SPI_SFRS->SPCR.SINTE = 1;
169 }
170 
174 static __INLINE void f_SPI_IRQDisable(void)
175 {
176  SPI_SFRS->SPCR.SINTE = 0;
177 }
178 
182 static __INLINE uint8_t f_SPI_ReadData(void)
183 {
184  return SPI_SFRS->SPDR;
185 }
186 
190 static __INLINE void f_SPI_WriteData(uint8_t data)
191 {
192  SPI_SFRS->SPDR = data;
193 }
194 
198 static __INLINE uint8_t f_SPI_GetStatus(void)
199 {
200  return SPI_SFRS->SPSR.SPSR;
201 }
202 
206 static __INLINE void f_SPI_ClearIRQ(void)
207 {
208  SPI_SFRS->SPSR.SINTF = 1;
209 }
210 
216 static __INLINE uint8_t f_SPI_TxFIFOFull(void)
217 {
218  return SPI_SFRS->SPSR.STXFF;
219 }
220 
226 static __INLINE uint8_t f_SPI_TxFIFOEmpty(void)
227 {
228  return SPI_SFRS->SPSR.STXFE;
229 }
230 
236 static __INLINE uint8_t f_SPI_RxFIFOFull(void)
237 {
238  return SPI_SFRS->SPSR.SRXFF;
239 }
240 
246 static __INLINE uint8_t f_SPI_RxFIFOEmpty(void)
247 {
248  return SPI_SFRS->SPSR.SRXFE;
249 }
250 
251 #endif /* __SPI_SFRS_H__ */
static __INLINE void f_SPI_ClearIRQ(void)
Clear SPI interrupt flag.
Definition: spi_sfrs.h:206
static __INLINE void f_SPI_IRQEnable(void)
Enable SPI interrupt.
Definition: spi_sfrs.h:166
uint8_t SPSR
Definition: spi_sfrs.h:40
static __INLINE uint8_t f_SPI_TxFIFOFull(void)
Check if transnmitter FIFO buffer full.
Definition: spi_sfrs.h:216
static __INLINE uint8_t f_SPI_TxFIFOEmpty(void)
Check if transnmitter FIFO buffer empty.
Definition: spi_sfrs.h:226
static __INLINE void f_SPI_SetPolarity(uint8_t Polarity)
Set SPI Polarity.
Definition: spi_sfrs.h:126
static __INLINE void f_SPI_IRQDelay(uint8_t cnt)
Set SPI interrupt delay cycles.
Definition: spi_sfrs.h:142
#define SPI_SFRS
The starting address of SPI SFRS.
Definition: spi_sfrs.h:57
A structure to represent Special Function Registers for SPI.
Definition: spi_sfrs.h:18
static __INLINE void f_SPI_SetMode(uint8_t mode)
Set SPI mode.
Definition: spi_sfrs.h:134
static __INLINE void f_SPI_Disable(void)
Disable SPI hardware module.
Definition: spi_sfrs.h:158
uint8_t SPDR
Definition: spi_sfrs.h:42
static __INLINE uint8_t f_SPI_GetStatus(void)
Get SPI status.
Definition: spi_sfrs.h:198
static __INLINE void f_SPI_ClockDiv(uint8_t div, uint8_t ext_div)
Set SPI clock divider.
Definition: spi_sfrs.h:109
uint8_t SPCR
Definition: spi_sfrs.h:28
static __INLINE uint8_t f_SPI_RxFIFOEmpty(void)
Check if receiver FIFO buffer empty.
Definition: spi_sfrs.h:246
static __INLINE uint8_t f_SPI_RxFIFOFull(void)
Check if receiver FIFO buffer full.
Definition: spi_sfrs.h:236
static __INLINE void f_SPI_WriteData(uint8_t data)
Write a byte to SPI data register.
Definition: spi_sfrs.h:190
uint8_t SPER
Definition: spi_sfrs.h:50
static __INLINE void f_SPI_Enable(void)
Enable SPI hardware module.
Definition: spi_sfrs.h:150
static __INLINE uint8_t f_SPI_ReadData(void)
Read a byte from SPI data register.
Definition: spi_sfrs.h:182
static __INLINE void f_SPI_SetPhase(uint8_t phase)
Set SPI phase.
Definition: spi_sfrs.h:118
static __INLINE void f_SPI_IRQDisable(void)
Disable SPI interrupt.
Definition: spi_sfrs.h:174